Debug circuit for an integrated circuit

ABSTRACT

An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.

BACKGROUND OF THE INVENTION

The present invention relates generally to integrated circuits, and,more particularly, to a method and circuit that allow debugging of anintegrated circuit.

Integrated circuits (IC) include various analog and digital circuitssuch as operational amplifiers, voltage regulators, voltage monitoringcircuits, sensors, logic circuits, and non-volatile memories. When an ICis powered on, these circuits are reset, i.e., set to correspondingpredefined states. A predefined state refers to a known and stablestate. To facilitate the reset of the circuits, the IC includes apower-on-reset (POR) generator and a reset controller. The POR generatorgenerates a POR signal to initiate a reset sequence. During the resetsequence, the reset controller initializes the aforementioned circuitsto corresponding predefined states.

Generally, the reset sequence includes multiple reset phases. Forexample, an IC may have four reset phases (first through fourth). In thefirst reset phase (also referred as a POR phase), circuits such asvoltage regulator circuits and voltage monitor circuits are initialized.The IC transitions to the second reset phase from one of the first resetphase, the third reset phase, the fourth reset phase, or an idle phase.The second reset phase is referred to as a clock initialization phaseduring which a clock signal is initialized, i.e., the IC receives apredefined minimum number of clock cycles of the clock signal from aclock signal source. Subsequently, the IC transitions from the secondreset phase to the third reset phase. In the third reset phase, anon-volatile memory such as a flash memory is initialized to a knownstate. Further, configuration information such as factory settings andboot code in the non-volatile memory are accessed by a processor of theIC during the third reset phase. The IC transitions to the fourth resetphase from either the third reset phase or the idle phase. In the fourthreset phase, the circuits perform self-tests and a few of the circuitsfetch and execute code from the non-volatile memory based on userrequirements.

During the reset sequence multiple circuits are initialized. If anycircuit is not initialized to a known state during the correspondingreset phase, the IC may remain in the reset phase. In such a scenario,the processor is not released from the reset sequence and the IC hangs.For example, in the first reset phase, if a voltage monitor circuit doesnot receive a voltage supply at a desired voltage level, then it may notde-assert and the IC will remain in the first reset phase. Similarly, inthe second reset phase, if the clock signal is inappropriatelyinitialized, an internal clock monitor circuit of the IC may notgenerate a clock-ok signal so there would be a failure of the clocksignal initialization, holding the IC in the second reset phase. If thememory is inappropriately initialized in the third reset phase, the ICwill remain in the third reset phase. As a result, the IC will be unableto transition to functional mode. Therefore, it is necessary to be ableto debug the IC when the IC is hung in one of the reset phases.Moreover, there is a need to determine in which reset phase of the resetsequence the IC is held, and the signals that have caused the IC to behung in the reset phase.

Existing debug circuits are inadequate for debugging the IC during thereset sequence. Further, it is undesirable to include dedicateddebugging input/output (IO) pins because that would increase area andcost. Also, increase in the number of dedicated debugging IO pins limitsthe number of IO pins available for functional purposes. Furthermore,when the IC is stuck in the reset phase, the processor may be unable toinitiate debugging. Hence, the control of debugging must be available toa user.

Therefore, it would be advantageous to have an IC that includes a debugcircuit for debugging the IC during a reset sequence.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description of the preferred embodiments of thepresent invention will be better understood when read in conjunctionwith the appended drawings. The present invention is illustrated by wayof example, and not limited by the accompanying figures, in which likereferences indicate similar elements.

FIG. 1 is a schematic block diagram of an integrated circuit (IC)including a debug circuit in accordance with an embodiment of thepresent invention;

FIG. 2 is a schematic block diagram of a debug enable circuit forgenerating a debug control signal in accordance with an embodiment ofthe present invention; and

FIG. 3 is a timing diagram that illustrates various signals generated bythe debug circuit and the debug enable circuit of FIGS. 1 and 2,respectively in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

The detailed description of the appended drawings is intended as adescription of the currently preferred embodiments of the presentinvention, and is not intended to represent the only form in which thepresent invention may be practiced. It is to be understood that the sameor equivalent functions may be accomplished by different embodimentsthat are intended to be encompassed within the spirit and scope of thepresent invention. As used herein, the term multiplexer has beenabbreviated as a mux.

In an embodiment of the present invention, an integrated circuitoperable in functional and debug modes and having an input/output (IO)pad is provided. The integrated circuit includes a pad control register,first through fifth logic gates, and a pad configuration register. Thepad control register stores pull-type select control and pull-enablecontrol bits and generates pull-type select control and pull-enablecontrol signals when the integrated circuit is in the functional mode.The first logic gate has a first input terminal for receiving a debugcontrol signal, a second input terminal for receiving a referencesignal, and an output terminal for generating a first signal when theintegrated circuit is in the debug mode. The second logic gate has afirst input terminal connected to the output terminal of the first logicgate for receiving the first signal, a second input terminal connectedto the pad control register for receiving the pull-type select controlsignal, and an output terminal for generating the first signal as apull-type select signal when the integrated circuit is in the debugmode. The third logic gate has a first input terminal for receiving afunctional signal of the integrated circuit, a second input terminal forreceiving the reference signal, and an output terminal for generating afunctional control signal when the integrated circuit is in the debugmode. The fourth logic gate has a first input terminal for receiving thedebug control signal, a second input terminal connected to the outputterminal of the third logic gate for receiving the functional controlsignal, and an output terminal for generating a second signal when theintegrated circuit is in the debug mode. The fifth logic gate, has afirst input terminal connected to the output terminal of the fourthlogic gate for receiving the second signal, a second input terminalconnected to the pad control register for receiving the pull-enablecontrol signal, and an output terminal for generating the second signalas a pull-enable signal when the integrated circuit is in the debugmode. The pad configuration register is connected to the outputterminals of the second and fifth logic gates for receiving thecorresponding pull-type select and pull-enable signals and the IO padfor configuring the IO pad in at least one of logic high, logic low, andhigh impedance states when the integrated circuit is in the debug mode.The at least one of the logic high, logic low, and high impedance statesof the IO pad indicate a state of the functional signal of theintegrated circuit.

In another embodiment of the present invention, an integrated circuitoperable in functional and debug modes and having an input/output (IO)pad is provided. The integrated circuit includes a multiplexer, aflip-flop, first through sixth logic gates, a pad control register, anda pad configuration register. The multiplexer has a first input terminalfor receiving a feedback signal, a second input terminal for receiving afuse signal, a select terminal for receiving a reset signal, and anoutput terminal for outputting at least one of the feedback and fusesignals when the integrated circuit is in the debug mode. The flip-flophas a first input terminal connected to the output terminal of themultiplexer for receiving at least one of the feedback and fuse signals,a second input terminal for receiving a power-on-reset signal, a clockinput terminal for receiving a clock signal, and an output terminal foroutputting at least one of the feedback and fuse signals when theintegrated circuit is in the debug mode. The output terminal of theflip-flop is connected to the first input terminal the input terminal ofthe multiplexer. The first logic gate has a first input terminalconnected to the output terminal of the flip-flop for receiving at leastone of the feedback and fuse signals, a second input terminal forreceiving the reset signal, a third input terminal for receiving acontrol signal, and an output terminal for generating a debug controlsignal when at least one of the feedback, fuse, reset, and controlsignals is at logic high state and the integrated circuit is in thedebug mode. The pad control register stores pull-type select control andpull-enable control bits and generates pull-type select control andpull-enable control signals when the integrated circuit is in thefunctional mode. The second logic gate has a first input terminalconnected to the output terminal of the first logic gate for receivingthe debug control signal, a second input terminal for receiving areference signal, and an output terminal for generating a first signalwhen the integrated circuit is in the debug mode. The third logic gate,having a first input terminal connected to the output terminal of thesecond logic gate for receiving the first signal, a second inputterminal connected to the pad control register for receiving thepull-type select control signal, and an output terminal for generatingthe first signal as a pull-type select signal when the integratedcircuit is in the debug mode. The fourth logic gate has a first inputterminal for receiving a functional signal of the integrated circuit, asecond input terminal for receiving the reference signal, and an outputterminal for generating a functional control signal when the integratedcircuit is in the debug mode. The fifth logic gate has a first inputterminal for receiving the debug control signal, a second input terminalconnected to the output terminal of the fourth logic gate for receivingthe functional control signal, and an output terminal for generating asecond signal when the integrated circuit is in the debug mode. Thesixth logic gate has a first input terminal connected to the outputterminal of the fifth logic gate for receiving the second signal, asecond input terminal connected to the pad control register forreceiving the pull-enable control signal, and an output terminal forgenerating the second signal as a pull-enable signal when the integratedcircuit is in the debug mode. The pad configuration register isconnected to the output terminals of the third and sixth logic gates forreceiving the corresponding pull-type select and pull-enable signals andthe IO pad for configuring the IO pad in at least one of logic high,logic low, and high impedance states when the integrated circuit is inthe debug mode. The at least one of the logic high, logic low, and highimpedance states of the IO pad indicate a state of the functional signalof the integrated circuit.

Various embodiments of the present invention provide an IC that isoperable in functional and debug modes and has an IO pad. The ICincludes a debug circuit, a debug enable circuit, a pad controlregister, and a pad configuration register. The IC is connected tocircuits such as voltage monitor and regulator circuits and circuitmonitoring circuits that generate functional signals to indicate thecorrect initialization of these circuits. The debug enable circuitreceives a control signal indicating a debug mode of the IC, a resetsignal and a fuse signal, and generates a debug control signal. Thedebug circuit receives the debug control signal from the debug enablecircuit, pull-type select and pull-enable control signals from the padcontrol register, a reference signal, and a functional signal andgenerates pull-enable and pull-type select signals. The padconfiguration register receives the pull-enable and pull-type selectsignals from the debug circuit and configures the IO pad in at least oneof logic high, logic low, and high impedance states. The logic high,logic low, and high impedance states of the IO pad indicate a state ofthe functional signal. The high impedance state of the IO pad indicatesthat the functional signal is in a correct state, i.e., the circuits arecorrectly initialized. When the IO pad is in the logic high state orlogic low state for a time period greater than a predetermined timeperiod, the debug circuit indicates that the functional signal is in anincorrect state, i.e., the circuits are incorrectly initialized. Theaforementioned debug mode corresponds to a reset phase of a resetsequence of the IC and the incorrect state of the functional signalindicates that the IC is held in the reset phase. The IO pad that isused along with the debug circuit to debug the IC is a general purposeIO pad (GPIO). The IC is debugged during the reset sequence of the IC bydetermining a logic state of the IO pad. The IO pad requires noredesigning for debugging the IC in the reset phase. Moreover, asadditional IO pads are not required in the IC, the area and cost thereofdoes not increase.

Referring now to FIG. 1, an integrated circuit (IC) 100 including adebug circuit 101 in accordance with an embodiment of the presentinvention is shown. The IC 100 is operable in functional and debugmodes. When the IC 100 is powered up, a power-on-reset (POR) generatorof the IC 100 (not shown) generates a POR signal and the IC 100transitions into a reset phase of a reset sequence. The reset sequenceincludes first through fourth reset phases.

The IC 100 includes multiple circuits such as voltage monitor andregulator circuits, and non-volatile memories (collectively not shown),that are initialized by a reset controller (explained in conjunctionwith FIG. 2) of the IC 100 during the reset phases of the resetsequence. Each circuit has a corresponding circuit monitoring circuit tomonitor the correct initialization of the circuit. When the circuits areinitialized during the corresponding reset phases, each monitoringcircuit generates a functional signal to indicate a successfulinitialization thereof. In an example, when a non-volatile memory suchas a flash memory (not shown) is initialized successfully, a flashmemory monitoring circuit (not shown) of the IC 100 generates a memoryinitialization status signal (hereinafter referred to as a flash readysignal) as the functional signal at logic high state.

However, when one of the abovementioned circuits is inappropriatelyinitialized in a corresponding reset phase, the IC 100 is held in thereset phase. The IC 100 is configured to operate in the debug mode ofoperation if the circuits are inappropriately initialized during thereset sequence and the debug circuit 101 debugs the IC 100 to identifythe inappropriately initialized circuits.

The IC 100 further includes a pad control register 102, a padconfiguration register 104, and an input/output (IO) pad 106.

The debug circuit 101 includes the first through fifth logic gates108-116. In an embodiment of the present invention, the first logic gate108 is an XNOR gate 108, the second and fourth logic gates 110 and 114are AND gates 110 and 114, respectively, and the third and fifth logicgates 112 and 116 are OR gates 112 and 116, respectively. The XNOR gate108 has a first input terminal connected to the circuit monitoringcircuit such as a flash memory monitoring circuit for receiving theflash ready signal as a functional signal and a second input terminalfor receiving a reference voltage signal, and an output terminal foroutputting a functional control signal. The reference voltage signal maybe generated by an internal bandgap reference voltage generator (notshown). When the IC 100 is in the debug mode, the XNOR gate 108 comparesa logic state of the functional signal with that of the referencesignal. The logic state of the reference signal corresponds to anincorrect logic state of the functional signal, i.e., a logic state thatindicates incorrect initialization of the circuits, during thecorresponding reset phase. The AND gate 110 has a first input terminalconnected to the output terminal of the XNOR gate 108 for receiving thefunctional control signal, a second input terminal for receiving a debugcontrol signal, and an output terminal for generating a second signal. Adebug enable circuit (explained in conjunction with FIG. 2), generatesthe debug control signal in the debug mode of operation of the IC 100.The pad control register 102 stores pull-type select and pull-enablecontrol bits and generates pull-enable control and pull-type selectcontrol signals. The OR gate 112 has a first input terminal connected tothe output terminal of the AND gate 110 for receiving the second signal,a second input terminal connected to the pad control register 102 forreceiving the pull-enable control signal, and an output terminal forgenerating a pull-enable signal. The AND gate 114 has a first inputterminal for receiving the reference signal, a second input terminal forreceiving the debug control signal, and an output terminal forgenerating a first signal. The OR gate 116 has a first input terminalconnected to the output terminal of the AND gate 114 for receiving thefirst signal, a second input terminal connected to the pad controlregister 102 for receiving the pull-type select control signal, and anoutput terminal for generating a pull-type select signal.

The pad configuration register 104 is connected to the output terminalsof the OR gates 112 and 116 for receiving the pull-type select andpull-enable signals and connected to the IO pad 106 for configuring theIO pad 106 in one of a logic high, logic low, and high impedance states.

The IO pad 106 includes pull-up and pull-down resistors 118 a and 118 b.A first terminal of the pull-up resistor 118 a is connected to a supplyvoltage V_(dd) and a second terminal thereof is connected to a firstterminal of the pull-down resistor 118 b. A second terminal of thepull-down resistor 118 b is connected to ground. The pad controlregister 102 generates pull-enable and pull-type select control signalsat logic low state during the reset phases of the reset sequence.

Referring now to FIG. 2, a debug enable circuit 200 for generating thedebug control signal connected to a reset controller 201 in accordancewith an embodiment of the present invention is shown. The resetcontroller 201 generates a reset process complete signal aftercompletion of the reset sequence. The reset controller 201 inverts thereset process complete signal to generate and provide a reset signal tothe debug enable circuit 200. The IC 100 may include multiple such debugcircuits 101 corresponding to multiple IO pads 106 of the IC 100. Thedebug enable circuit 200 is connected to the debug circuits 101. Thedebug enable circuit 200 includes a multiplexer 202 or mux 202, aflip-flop 204, and a logic gate 206. In an embodiment of the presentinvention, the mux 202 is a 2:1 mux and the logic gate 206 is an ANDgate 206. The flip-flop 204 is a D-type positive-edge triggeredflip-flop.

The mux 202 has a first input terminal connected to a fuse register (notshown) for receiving a fuse signal, a second input terminal forreceiving a feedback signal, a select terminal connected to the resetcontroller 201 for receiving the reset signal, and an output terminalfor outputting at least one of the fuse and feedback signals. When theIC 100 is in the debug mode, the fuse register stores a fuse bit that isat logic high state. The flip-flop 204 has a first input terminalconnected to the output terminal of the mux 202 for receiving at leastone of the fuse and feedback signals, a second input terminal connectedto the POR generator (not shown) for receiving the POR signal, a clockinput terminal for receiving a clock signal, and an output terminal foroutputting at least one of the fuse and feedback signals. The outputterminal of the flip-flop 204 is connected to the first input terminalof the mux 202. The AND gate 206 has a first input terminal connected tothe output terminal of the flip-flop 204 for receiving at least one ofthe fuse and feedback signals, a second input terminal connected to thereset controller 201 for receiving the reset signal, a third inputterminal for receiving a control signal, and an output terminal forgenerating the debug control signal.

Referring now to FIG. 3, a timing diagram illustrating the fuse signal,the reset signal, the control signal, the clock signal, the POR signal,the debug control signal, the reset phases of the reset sequence, thereference signal, the pull-type signal, the pull-enable signal, theflash ready signal, and the state of the IO pad 106 of the IC 100 isshown. Generally, when the IC 100 is powered up (at time instance t0),the functional signals are at logic low state. However, when thefunctional signals fail to change the logic state thereof in thesubsequent reset phases, the IC 100 is held in the corresponding resetphase. In the example, the flash ready signal is desired to be at logiclow state during the POR phase, i.e., the first reset phase, and thesecond reset phase (during time period t0-t9). The flash ready signaltoggles from logic low to logic high state during the third reset phase(at time instance t9) and is at logic high state thereon during thereset phases 2 and 3 (time instance t9 to t16). When the flash readysignal is at logic low state during the second and third reset phases(time period t9-t16), the IC 100 is held in the reset sequence. Thus,the reference signal is set at logic low state, as shown in FIG. 3, todetermine the logic state of the flash ready signal.

In operation, when the IC 100 is powered on, the POR generator generatesthe POR signal at logic low state and the IC 100 is in the first resetphase (during time period t0-t1). The flip-flop 204 is a set-typeflip-flop and has an active low second input terminal. Thus, the secondinput terminal of the flip-flop 204 receives the POR signal at logic lowstate and the output terminal thereof provides a logic high signal tothe first input terminal of the AND gate 206. The reset controller 201generates the reset process complete signal to indicate the completionof the reset sequence. Subsequently, the reset controller 201 alsogenerates the reset signal. When the IC 100 is in one of the resetphases of the reset sequence, the reset process complete signal is atlogic low state and the reset signal is at logic high state (during timeperiod t0-t16). When the reset sequence is complete, the reset processcomplete signal is at logic high state and the reset signal is at logiclow state (during time period t16-t18).

When the IC 100 is in the first reset phase, the second input terminalof the AND gate 206 receives the reset signal at logic high state(during time period t0-t2). The third input terminal of the AND gate206, is connected to a test enable IO pad (not shown) of the IC 100 andreceives the control signal therefrom. The test enable IO pad is atlogic high state and thus, the control signal is at logic high state(during time period t0-t16). A user may control the test enable IO pad.Thus, the control of debugging the IC 100 is available with the user.When the IC 100 is in the first reset phase, the third input terminal ofthe AND gate 206 receives the control signal at logic high state (duringtime period t0-t2). Thus, during the first reset phase, the AND gate 206receives the logic high signal from the flip-flop 204, the logic highreset signal, and the logic high control signal and generates the debugcontrol signal at logic high state (during time period t0-t2).

During the first reset phase (during time period t0-t2), when the flashready and reference signals are at logic low states, the XNOR gate 108generates the functional control signal at logic high state. The ANDgate 110 receives the logic high functional control and debug controlsignals and generates the second signal at logic high state. The OR gate112 receives the logic high second signal and logic low pull-enablecontrol signal and generates the pull-enable signal at logic high state(at time instance t0). The AND gate 114 receives the logic high debugcontrol signal and the logic low reference signal and generates thefirst signal at logic low state. The OR gate 112 receives the logic lowfirst and pull-type select control signals and generates the pull-typeselect signal at logic low state (at time instance t0). The padconfiguration register 104 receives the logic high pull-enable signaland logic low pull-type select signal and configures the IO pad 106 to alogic low state (during time period t0-t2). In the IO pad 106, thepull-down resistor 118 b receives the logic high pull-enable signal andlogic low pull-type select signal and weakly pulls down the IO pad 106to ground. The logic low state of the IO pad 106 indicates that theflash ready signal is at logic low state. Although the IO pad 106 is inlogic low state, the IC 100 is not held in the first reset phase, aslogic low state is the desired logic state of the flash ready signal inthe first reset phase.

After the completion of the first reset phase, the POR generatorgenerates the POR signal at logic high state and the flip-flop 204receives the logic high POR signal (at time instance t1). Thus theflip-flop 204 outputs at least one of the fuse and feedback signals. Themux 202 outputs the feedback signal based on the logic high reset signal(during time period t2-t16). The flip-flop 204 receives the feedbacksignal which is the logic high signal and provides the feedback signalto the first input terminal of the AND gate 206 (during time periodt2-t16). During the first through fourth reset phases, the AND gate 206receives the logic high reset and logic high control signals, and thelogic high feedback signal from the flip-flop 204, and generates thedebug control signal at logic high state (during time period t2-t16).

When the IC 100 transitions into the third reset phase, the non-volatilememories such as the flash memory are initialized and the flash readysignal toggles from logic low to logic high state (at time instance t9).The XNOR gate 108 receives the logic high flash ready and logic lowreference signals (at time instance t9) and generates the functionalcontrol signal at logic low state. The AND gate 110 receives the logiclow functional control signal and the logic high debug control signaland generates the second signal at logic low state. The OR gate 112receives the logic low second and pull-enable control signals andgenerates the pull-enable signal at logic low state (at time instancet9). The AND gate 114 receives the logic high debug control signal andthe logic low reference signal and generates the first signal at logiclow state. The OR gate 116 receives the logic low first and pull-typeselect control signals and generates the pull-type select signal atlogic low state (at time instance t9). As the pull-enable signal is atlogic low state, the pad configuration register 104 configures the IOpad 106 in the high impedance state (at time instance t9). The highimpedance state of the IO pad 106 indicates that the flash ready signalis at the desired logic state. However, when the flash ready signalfails to toggle from logic low to logic high state and is at logic lowstate in the second and third reset phases, the pad configurationregister 104 configures the IO pad 106 to logic low state. The logic lowstate of the IO pad 106 during the second and third reset phasesindicates an undesired logic state of the flash ready signal.

The first through fourth reset phases have corresponding predeterminedtime periods. When the IO pad 106 is in the logic low state for thefirst through fourth reset phases, i.e., for a time period greater thanthe predetermined time periods for the first and second reset phases,the IC 100 is held in the reset sequence. It will be apparent to thoseskilled in the art that the undesired logic state of some of thefunctional signals may be logic high state during the reset phases. Thereference signal is then set to logic high state and the padconfiguration register 104 configures the IO pad 106 in logic high statewhen the functional signal is in the undesired logic state.

After the completion of the reset sequence, the reset controller 201generates the reset process complete signal at logic high state andhence, the reset signal is at logic low state (during time instancet16-t18). The mux 202 outputs the fuse signal based on the logic lowreset signal. The flip-flop 204 receives the fuse signal and providesthe fuse signal to the first input terminal of the AND gate 206.However, as the reset signal at the second input terminal of the ANDgate 206 is at logic low state, the debug control signal is at logic lowstate and the debug circuit 101 is disabled (during time periodt16-t18). For the subsequent reset sequence, the fuse signal determinesthe logic state of the debug control signal. When the IC 100 transitionsinto any of the subsequent reset sequences, the reset controller 201generates the reset process complete signal at logic low state and thereset signal is at logic high state (during time period t2-t16). Whenthe fuse signal is at logic high state, consequently, the feedbacksignal is at logic high state. The mux 202 outputs the feedback signalbased on the logic high reset signal. The flip-flop 204 receives thelogic high feedback signal and provides the logic high feedback signalto the first input terminal of the AND gate 206. The AND gate 206receives the logic high reset and control signals and generates thedebug control signal at logic high state (during time period t2-t16).The debug enable circuit 200 provides an option to the user to disablethe debug circuit 101 by way of the test enable IO pad. In an alternateembodiment of the present invention, the AND gate 206 has the first andsecond input terminals for receiving at least one of the fuse andfeedback signals and the reset signal, respectively, and an outputterminal for generating the debug control signal based on either of thefuse or feedback signals and the reset signal.

As the IC 100 is debugged during the reset sequence by determining alogic state of the IO pad 106, the IO pad 106 does not requireadditional redesigning for debugging. Further, absence of additionaldedicated debugging IO pads restrains any increase in the area and costof the IC 100. As the debug circuit 101 is a standard circuit anddifferent functional signals require only the logic state of thereference signal to be altered, the implementation of the debug mode inthe IC 100 is simple. The number of IO pads 106 that are connected to acorresponding debug circuit 101 is based on the number of the functionalsignals that need to be observed. If the IO pad 106 is connected to anIO pad of an external IC and the debug circuit 101 controls the IO pad106 when the IC 100 is in the debug mode, contention is avoided as thepull-up and pull-down resistors 118 a and 118 b weakly pull up and pulldown the IO pad 106, respectively. When the IC 100 is in the functionalmode, the debug enable circuit 200 disables the debug circuit 101 andhence, the IO pad 106 is inaccessible by the debug circuit 101. Thus,the external IC can control the IO pad 106 without any contention inboth the debug and functional modes, ensuring smooth and error-freecommunication between the IC 100 and the external IC.

It will be understood by those of skill in the art that the same logicalfunction may be performed by different arrangements of logic gates, orthat logic circuits operate using either positive or negative logicsignals. Therefore, variations in the arrangement of some of the logicgates described above should not be considered to depart from the scopeof the present invention.

While various embodiments of the present invention have been illustratedand described, it will be clear that the present invention is notlimited to these embodiments only. Numerous modifications, changes,variations, substitutions, and equivalents will be apparent to thoseskilled in the art, without departing from the spirit and scope of thepresent invention, as described in the claims.

1. An integrated circuit operable in functional and debug modes and having an input/output (IO) pad, comprising: a pad control register for storing pull-type select control and pull-enable control bits and generating pull-type select control and pull-enable control signals when the integrated circuit is in the functional mode; a first logic gate having a first input terminal for receiving a debug control signal, a second input terminal for receiving a reference signal, and an output terminal for generating a first signal when the integrated circuit is in the debug mode; a second logic gate having a first input terminal connected to the output terminal of the first logic gate for receiving the first signal, a second input terminal connected to the pad control register for receiving the pull-type select control signal, and an output terminal for generating the first signal as a pull-type select signal when the integrated circuit is in the debug mode; a third logic gate having a first input terminal for receiving a functional signal of the integrated circuit, a second input terminal for receiving the reference signal, and an output terminal for generating a functional control signal when the integrated circuit is in the debug mode; a fourth logic gate having a first input terminal for receiving the debug control signal, a second input terminal connected to the output terminal of the third logic gate for receiving the functional control signal, and an output terminal for generating a second signal when the integrated circuit is in the debug mode; a fifth logic gate having a first input terminal connected to the output terminal of the fourth logic gate for receiving the second signal, a second input terminal connected to the pad control register for receiving the pull-enable control signal, and an output terminal for generating the second signal as a pull-enable signal when the integrated circuit is in the debug mode; and a pad configuration register, connected to the output terminals of the second and fifth logic gates for receiving the corresponding pull-type select and pull-enable signals, and to the IO pad for configuring the IO pad in at least one of logic high, logic low, and high impedance states when the integrated circuit is in the debug mode, wherein at least one of the logic high, logic low, and high impedance states of the IO pad indicates a state of the functional signal of the integrated circuit.
 2. The integrated circuit of claim 1, further comprising: a multiplexer having a first input terminal for receiving a feedback signal, a second input terminal for receiving a fuse signal, a select terminal for receiving a reset signal, and an output terminal for outputting at least one of the feedback and fuse signals when the integrated circuit is in the debug mode; a flip-flop having a first input terminal connected to the output terminal of the multiplexer for receiving at least one of the feedback and fuse signals, a second input terminal for receiving a power-on-reset signal, a clock input terminal for receiving a clock signal, and an output terminal for outputting at least one of the feedback and fuse signals when the integrated circuit is in the debug mode, wherein the output terminal of the flip-flop is connected to the first input terminal of the multiplexer; and a sixth logic gate having a first input terminal connected to the output terminal of the flip-flop for receiving at least one of the feedback and fuse signals therefrom, a second input terminal for receiving the reset signal, a third input terminal for receiving a control signal, and an output terminal for generating the debug control signal when at least one of the feedback, fuse, reset, and control signals is at a logic high state and the integrated circuit is in the debug mode.
 3. The integrated circuit of claim 2, wherein the first, second, third, fourth, fifth, and sixth logic gates each comprises at least one of an AND gate, an OR gate, and an XNOR gate.
 4. The integrated circuit of claim 1, wherein the state of the functional signal is an incorrect state when the IO pad is either in a logic high state for a time period greater than a predetermined time period and a logic low state for a time period greater than the predetermined time period.
 5. The integrated circuit of claim 1, wherein the pad configuration register places the IO pad in a logic high state when the pull-type select and pull-enable signals are at a logic high state, wherein the logic high state of the IO pad indicates that the functional signal is in a logic high state.
 6. The integrated circuit of claim 1, wherein the pad configuration register places the IO pad in a logic low state when the pull-type select and pull-enable signals are in logic low and high states, respectively, wherein a logic low state of the IO pad indicates that the functional signal is in a logic low state.
 7. The integrated circuit of claim 1, wherein the pad configuration register configures the IO pad in a high impedance state when the pull-enable signal is in a logic low state, wherein the high impedance state of the IO pad indicates a correct state of the functional signal.
 8. The integrated circuit of claim 1, wherein the IO pad includes: a pull-up resistor having a first terminal connected to a supply voltage; and a pull-down resistor having a first terminal connected to a second terminal of the pull-up resistor and a second terminal connected to ground.
 9. The integrated circuit of claim 8, wherein the pad configuration register configures the IO pad such that the pull-up resistor pulls up a voltage of the IO pad to the supply voltage, thereby placing the IO pad in a logic high state, and the pull-down resistor pulls down a voltage of the IO pad to ground, thereby placing the IO pad in a logic low state when the integrated circuit is in the debug mode.
 10. The integrated circuit of claim 1, wherein the debug mode corresponds to a reset sequence of the integrated circuit.
 11. An integrated circuit operable in functional and debug modes and having an input/output (IO) pad, comprising: a multiplexer having a first input terminal for receiving a feedback signal, a second input terminal for receiving a fuse signal, a select terminal for receiving a reset signal, and an output terminal for outputting at least one of the feedback and fuse signals when the integrated circuit is in the debug mode; a flip-flop having a first input terminal connected to the output terminal of the multiplexer for receiving at least one of the feedback and fuse signals, a second input terminal for receiving a power-on-reset signal, a clock input terminal for receiving a clock signal, and an output terminal for outputting at least one of the feedback and fuse signals when the integrated circuit is in the debug mode, wherein the output terminal of the flip-flop is connected to the first input terminal of the multiplexer; a first logic gate having a first input terminal connected to the output terminal of the flip-flop for receiving at least one of the feedback and fuse signals, a second input terminal for receiving the reset signal, a third input terminal for receiving a control signal, and an output terminal for generating a debug control signal when at least one of the feedback, fuse, reset, and control signals is at logic high state and the integrated circuit is in the debug mode; a pad control register for storing pull-type select control and pull-enable control bits and generating pull-type select control and pull-enable control signals when the integrated circuit is in the functional mode; a second logic gate having a first input terminal connected to the output terminal of the first logic gate for receiving the debug control signal, a second input terminal for receiving a reference signal, and an output terminal for generating a first signal when the integrated circuit is in the debug mode; a third logic gate having a first input terminal connected to the output terminal of the second logic gate for receiving the first signal, a second input terminal connected to the pad control register for receiving the pull-type select control signal, and an output terminal for outputting the first signal as a pull-type select signal when the integrated circuit is in the debug mode; a fourth logic gate having a first input terminal for receiving a functional signal of the integrated circuit, a second input terminal for receiving the reference signal, and an output terminal for generating a functional control signal when the integrated circuit is in the debug mode; a fifth logic gate having a first input terminal for receiving the debug control signal, a second input terminal connected to the output terminal of the fourth logic gate for receiving the functional control signal, and an output terminal for generating a second signal when the integrated circuit is in the debug mode; a sixth logic gate having a first input terminal connected to the output terminal of the fifth logic gate for receiving the second signal, a second input terminal connected to the pad control register for receiving the pull-enable control signal, and an output terminal for generating the second signal as a pull-enable signal when the integrated circuit is in the debug mode; and a pad configuration register, connected to the output terminals of the third and sixth logic gates for receiving the corresponding pull-type select and pull-enable signals and the IO pad for configuring the IO pad in at least one of logic high, logic low, and high impedance states when the integrated circuit is in the debug mode, whereby at least one of the logic high, logic low, and high impedance states of the IO pad indicate a state of the functional signal of the integrated circuit.
 12. The integrated circuit of claim 11, wherein the state of the functional signal is an incorrect state when the IO pad is in at least one of logic high state for a time period greater than a predetermined time period and logic low state for a time period greater than the predetermined time period.
 13. The integrated circuit of claim 11, wherein the pad configuration register configures the IO pad in logic high state when the pull-type select and pull-enable signals are at logic high state, whereby logic high state of the IO pad indicates that the functional signal of the integrated circuit is at logic high state.
 14. The integrated circuit of claim 11, wherein the pad configuration register configures the IO pad in logic low state when the pull-type select and pull-enable signals are at logic low and high states, respectively, whereby logic low state of the IO pad indicates that the functional signal of the integrated circuit is at logic low state.
 15. The integrated circuit of claim 11, wherein the pad configuration register configures the IO pad in high impedance state when the pull-enable signal is at logic low state, whereby high impedance state of the IO pad indicates a correct state of the functional signal of the integrated circuit.
 16. The integrated circuit of claim 11, wherein the first, second, third, fourth, fifth, and sixth logic gates each comprises at least one of an AND gate, an OR gate, an XOR gate, a NOT gate, and an XNOR gate.
 17. The integrated circuit of claim 11, wherein the IO pad includes: a pull-up resistor having a first terminal connected to a supply voltage, and a pull-down resistor having a first terminal, connected to a second terminal of the pull-up resistor and a second terminal connected to ground.
 18. The integrated circuit of claim 17, wherein the pad configuration register configures the IO pad such that the pull-up resistor pulls up a voltage of the IO pad to the supply voltage, thereby configuring the IO pad in logic high state, and the pull-down resistor pulls down a voltage of the IO pad to ground, thereby configuring the IO pad in logic low state when the integrated circuit is in the debug mode.
 19. The integrated circuit of claim 11, wherein the multiplexer outputs the feedback signal at logic high state when the power-on-reset signal is at logic low state and the reset signal is at logic high state.
 20. The integrated circuit of claim 11, wherein the functional signal of the integrated circuit comprises at least one of a clock initialization status signal and a memory initialization status signal. 